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Self Checked Error Correction Code Generator, ECC Comparer Error Syndrome Decoder and Data Bit Corrector

IP.com Disclosure Number: IPCOM000077933D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Boden, RC: AUTHOR

Abstract

In data-processing systems with error correction, ECC bits are generated from a data block comprising bytes and are then appended thereto. An overall word parity bit is generated and also appended, and the entire data entity is stored. Upon reading the data entity from storage, the ECC bits are generated from the data being read and are compared with the ECC bits read from storage to detect a transfer error and establish the location of a faulty bit, if an error is indicated. To guard against double errors, the overall word parity bit is compared with a new overall word parity bit generated from the data block and the ECC bits read from storage. For example, it can be assumed that there are seven ECC bits C0, C1, C2, ..., C6, and the overall parity bit can be designated CT.

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Self Checked Error Correction Code Generator, ECC Comparer Error Syndrome Decoder and Data Bit Corrector

In data-processing systems with error correction, ECC bits are generated from a data block comprising bytes and are then appended thereto. An overall word parity bit is generated and also appended, and the entire data entity is stored. Upon reading the data entity from storage, the ECC bits are generated from the data being read and are compared with the ECC bits read from storage to detect a transfer error and establish the location of a faulty bit, if an error is indicated. To guard against double errors, the overall word parity bit is compared with a new overall word parity bit generated from the data block and the ECC bits read from storage.

For example, it can be assumed that there are seven ECC bits C0, C1, C2, ..., C6, and the overall parity bit can be designated CT. A single-error correcting, double-error detecting Hamming code could there fore be used.

Although the CT bit represents the parity of all data bits plus the ECC bits, it is typically independently generated solely from the data bits. This is done by forming it from a parity count of 1's in only those data bit positions which, if equal to 1, will result in the changing of an even number of ECC bits. (The even number of ECC bits changed plus the bit generating them, form an odd number of overall word bit changes to be accounted for by the overall parity bit.) In addition, the circuitry involved in ECC bit generation which could by failure affect two ECC bits can be made self-checked by involving it in the generation of byte parities, which are typically required for the process of checking the transfer of data into the ECC area. SELF-CHECKING FOR THE ECC GENERATOR.

In view of the above, an ECC generator can be implemented which will be self-checked on read as well as write operations. Given that the parity of all ECC bits can be taken at the output of the ECC generator, it is only necessary to compare this parity with the overall byte parity produced by the ECC generator, to detect any single failure of either the code generator or the CT bit generator. SELF-CHECKING FOR THE ECC COMPARER, ERROR SYNDROME DECODER, AND DATA BIT CORRECTOR. Decode Check.

Referring to the figure, bus 1 transmits the ECC bits received during data transfer while bus 3 transmits the ECC bits generated on reading. Respective pairs of received and generated ECC bits are connected to exclusive-Or compare circuits S1, S2, ..., S6. The ou...