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Browse Prior Art Database

Emulator Instruction Retry

IP.com Disclosure Number: IPCOM000077946D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Magrisso, IB: AUTHOR

Abstract

Emulator instruction retry is provided in a data-processing system when intermittent hardware errors occur. The data processing system in Fig. 1 includes conventional main storage 5 for containing the emulator program and the data to be emulated. It also includes storage address register 6, storage data register 7, operand registers 11 and 12, arithmetic and logic unit (ALU) 13 and local storage registers (LSR's) 30. In addition to the conventional hardware, the system also includes retry latch 10 and go latch 15.

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Emulator Instruction Retry

Emulator instruction retry is provided in a data-processing system when intermittent hardware errors occur. The data processing system in Fig. 1 includes conventional main storage 5 for containing the emulator program and the data to be emulated. It also includes storage address register 6, storage data register 7, operand registers 11 and 12, arithmetic and logic unit (ALU) 13 and local storage registers (LSR's) 30. In addition to the conventional hardware, the system also includes retry latch 10 and go latch 15.

When an intermittent hardware error occurs as detected by error detection circuit 20 of controls 25, a machine check interrupt routine takes control over the emulator routine. The state of latch 15 is checked by the interrupt routine and if latch 15 is still set, it indicates that the instruction can be retried and the machine check interrupt routine sets the emulator program controls to retry the emulator instruction. If latch 15 is in the reset state, it indicates that emulation process is at a point in its sequence where information required to enable retry of the instruction has been destroyed. Thus, the instruction is not retried and the processing system stops with a processor check indicated. Also, if any intermittent hardware error occurs while the machine check interrupt routine is in control, the processing system will stop with a machine check indication.

During the emulation instruction sequence, the emulator address register 35 of local storage registers 30 starts the execution at address Z, as shown in Fig. 2. At this address, the emulator initializes status and certain registers including the machine...