Browse Prior Art Database

Control for Microprocessor

IP.com Disclosure Number: IPCOM000078023D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Crockett, PN: AUTHOR [+3]

Abstract

This is apparatus for generating starting addresses of subroutines in a control store driven microprogrammed computer. The apparatus includes an address stack array 10, an address adder 12, address mixing and logic 14, and various busses. All modules of the computer address the stack by the communication bus.

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Control for Microprocessor

This is apparatus for generating starting addresses of subroutines in a control store driven microprogrammed computer. The apparatus includes an address stack array 10, an address adder 12, address mixing and logic 14, and various busses. All modules of the computer address the stack by the communication bus.

In normal operation, the present address is read out of the address stack 10 link address area to the adder 12, updated by information on the communication bus, and written back into the stack via loop 16. The address is also made available to the control store for addressing a subroutine.

Branching within a subroutine is accomplished by selecting either the emit field, adder output or communication bus to modify the present address by adder
12. A subroutine may be entered directly by energizing the emit field, adder output or communication bus input to the logic block 14, which causes the stack 10 to be addressed thereby, instead of by the present address from adder 12. Thus, a subroutine is entered without losing time.

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