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Incrementing/Decrementing Binary Counter/Register/Decoder

IP.com Disclosure Number: IPCOM000078027D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 4 page(s) / 84K

Publishing Venue

IBM

Related People

Mattern, RC: AUTHOR

Abstract

A basic two-bit counter is illustrated in Fig. 1 and consists of a two decode flip-flop circuit 50, associated control logic 16, decode logic 70 and advance-carry-borrow logic 36. The two-bit counter may be loaded with gated in bits to register a value, be incremented or decremented to count forward or backward, and provide out bits which may also be decoded onto one of four output lines. The advance-carry-borrow logic 36 controls activation of a clock gate and enables two-bit counters to be connected to form different configurations of register-counter-decoders, by receiving and processing a carry or borrow from a lower order two-bit counter and propagating a carry or borrow to a higher order two-bit counter, as required.

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Incrementing/Decrementing Binary Counter/Register/Decoder

A basic two-bit counter is illustrated in Fig. 1 and consists of a two decode flip-flop circuit 50, associated control logic 16, decode logic 70 and advance- carry-borrow logic 36. The two-bit counter may be loaded with gated in bits to register a value, be incremented or decremented to count forward or backward, and provide out bits which may also be decoded onto one of four output lines. The advance-carry-borrow logic 36 controls activation of a clock gate and enables two-bit counters to be connected to form different configurations of register-counter-decoders, by receiving and processing a carry or borrow from a lower order two-bit counter and propagating a carry or borrow to a higher order two-bit counter, as required. An example of a register-counter-decoder consisting of three interconnected two-bit counters is shown in Fig. 2.

The two bit counter may be reset by applying a signal via the reset line to the respective reset inputs of the decode flip-flops (FFs) 46 and 48, causing negative output signals to be produced indicating a zero (00) condition. A value may be loaded into the FFs under control of the AND circuits 2 and 4 of the control circuit 16 by raising the level of the load line to gate the input bits to set the FFs, in accordance with the values (0 or 1) of the in bits.

The two-bit counter may be initialized to a zero (00) condition, as above, and then incremented to provide a forward count or a starting predetermined value may be loaded, as above, which may then be incremented or decremented depending upon the application desired. The level of the signal on the increment/decrement line to the advance-carry-borrow logic 36 determines whether the counter is incremented or decremented. Thus, assuming that the counter has been reset, a positive signal is maintained on the carry line and the level of the increment/ decrement line is raised to condition the counter for a forward count. In the case of a single stage two-bit counter or the lowest order stage of a group of interconnected two-bit counters, the carry and borrow lines are maintained at positive levels. With the counter being initially reset, both FFs 46 and 48 provide negative signals which are applied to the out bit lines and to the decoder 70. The negative signals are applied to selectively decondition each of the AND circuits 60, 64 and 68 and are inverted by inverters 52 and 54 to positive signals which render AND circuit 56 effective to apply a positive signal to the 00 line reflecting the zero condition of the counter. FF 46 also applies the negative output signal to the inverter 44 where it is inverted to a positive signal, which is applied to the set condition input of the FF 46. FF 46 is thereby conditioned to be set on upon the application of a clock gate signal. FF 48 also applies the negative output signal to one input of exclusive OR circuit 40 and is inverted by inverter 38 and applied...