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Circuit Useable as Storage Cell or Detector Amplifier Cell

IP.com Disclosure Number: IPCOM000078028D
Original Publication Date: 1972-Oct-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Klepp, H: AUTHOR [+2]

Abstract

This cell consists of nonlinearly loaded diodes D1 and D2, direct coupled transistor latch (T1 and T2), the state of which is steered at low (ma) and sensed at high (ma+) currents. The storage cell is dynamic; its time is controlled by the erase pulse via diodes D3 and D4. The sense resistors R1 and R2 are external to the monolithic amplifier structure proper. This complete cell, when properly designed, can be built into only two isolation regions.

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Circuit Useable as Storage Cell or Detector Amplifier Cell

This cell consists of nonlinearly loaded diodes D1 and D2, direct coupled transistor latch (T1 and T2), the state of which is steered at low (ma) and sensed at high (ma+) currents. The storage cell is dynamic; its time is controlled by the erase pulse via diodes D3 and D4. The sense resistors R1 and R2 are external to the monolithic amplifier structure proper. This complete cell, when properly designed, can be built into only two isolation regions.

The amplifier cell functions as follows: the interrogate current is steered, in the absence of positive data, into T1 by the steering voltage, V (approximately +5 mv), which is needed to overcome the various build tolerances in the matched diode and transistor pairs. This state is arbitrarily defined as a logical "zero" and is sensed on R1 and R2. positive data input current (high-source impedance) overcomes the effect of V, and upon the application of the interrogate signal it is sensed as a "one" on R1 and R2, the voltage at R2 being less than the voltage at R1.

The state of the latch, "zero" or "one" can be maintained, without power, as a charge on the T1 and T2 nodal capacitances for a period of t sec after termination of the interrogate pulse. The length of t is determined by R x C nodal, where R is the total leakage paths on C, including the data input source impedance; typically in the hundreds of milliseconds. The length of t can be actively shortened b...