Browse Prior Art Database

High Speed Push Pull Driver

IP.com Disclosure Number: IPCOM000078032D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Barsuhn, HE: AUTHOR [+4]

Abstract

This push-pull driver is designed to drive high-capacitive loads at very high-switching speeds. It offers particular advantages, for example, in connection with large field-effect transistor (FET) memories with their inherent capacitive properties.

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High Speed Push Pull Driver

This push-pull driver is designed to drive high-capacitive loads at very high- switching speeds. It offers particular advantages, for example, in connection with large field-effect transistor (FET) memories with their inherent capacitive properties.

When input A is more negative than VRef, T7 is off and CLoad is charged up via R1 and Darlington stage T6, T5. Switching A to a more positive level than VRef leads to the load capacitance being discharged at high speed. As T7 is conducting T6 is turned off. T8 is off, so that T2 is turned on via R2 and emitter- follower T1. The collector current of T2 first discharges the base of T5 and is subsequently drawn from CLoad via D2. The associated emitter current of T2 supplies the high-base drive for output power transistor T3 which then discharges the load capacitance.

After CLoad has been discharged, driving stage (R2, T1, T2), is automatically turned off, separating the base drive from T3. The DC down level is maintained by a pick-a-pack transistor T4.

The particular advantages and circuit principles are: - Discharging of the load capacitance is controlled by the voltage across the capacitance proper, thus considerably reducing power dissipation. - Transistor saturation in the driver prestage circuit is eliminated, thus increasing the switching speed. - Feedback loop from output to base of output driver transistor T3 supports the discharge operation, thus ensuring a higher switching speed.

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