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Memory Bit Driver

IP.com Disclosure Number: IPCOM000078048D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Jacobson, EC: AUTHOR [+2]

Abstract

The input devices, field-effect transistors (FET) T1, T2, ..., T6, accept the logic pulses at transistor-transistor logic (T/2/L) levels, from the central processing unit, and logically interpret them. With the logic pulses at the T/2/L "up" levels, the voltages at points A and B are below the threshold voltages of T7, T12, T13, and T14. In addition, the restore devices, T15 and T16 are "on", biasing the bit lines at the V(B) voltage.

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Memory Bit Driver

The input devices, field-effect transistors (FET) T1, T2, ..., T6, accept the logic pulses at transistor-transistor logic (T/2/L) levels, from the central processing unit, and logically interpret them. With the logic pulses at the T/2/L "up" levels, the voltages at points A and B are below the threshold voltages of T7, T12, T13, and T14. In addition, the restore devices, T15 and T16 are "on", biasing the bit lines at the V(B) voltage.

During a read or write operation, the module select (M/S) pulse drops to the T/2/L "down" level, turning devices T2, T4, T15, and T16, "off". If the read/write (R/W) pulse drops to its "down" level, during a write cycle, the voltages at points A and B are controlled by the data-in pulse. If the data-in pulse remains at the "up" level, the voltage of point B stays below the threshold of T12 and T13. The voltage at point A, however, rises towards +V, turning "on" T7 and T14. T7 will pull bit line B1 to ground potential, while T14 will maintain bit line B Phi at its V(B) voltage, thereby writing into a memory cell connected between the bit lines. If the data-in pulse drops to its "down" level, the voltage at point B will rise towards +V, causing bit line B Phi to be pulled to ground potential and bit line B1 to be held at the V(B) voltage. In this case, the voltage at point A will be held below the threshold voltages of T7 and T14, by device T3. This will cause a second state to be written into a cell connected betwee...