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FET Polarity Hold Circuit

IP.com Disclosure Number: IPCOM000078059D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR

Abstract

This polarity hold circuit provides an output data signal which is the complement of the input data signal at the clock voltage time. In the interval between clock pulses, the output data signal remains unchanged irrespective of changes in the input data signal.

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FET Polarity Hold Circuit

This polarity hold circuit provides an output data signal which is the complement of the input data signal at the clock voltage time. In the interval between clock pulses, the output data signal remains unchanged irrespective of changes in the input data signal.

The described function is achieved by the circuit shown in the drawing which is suitable for high density, large scale integration applications utilizing a relatively few number of field-effect transistors (FETs). The clock data signal on input line 1 is normally "down". When the clock signal is "up", the data signal input on line 2 is coupled through conducting FET 3 to line 4. For example, if the data signal is low when the clock signal is high, the signal on line 4 is low, turning off FET 5 and allowing the output data signal on line 6 to rise to voltage V through FET load device 7.

The output signal on line 6 remains high when the clock signal on line 1 is low, irrespective of changes in the data signal on line 2. Should the data signal go up when the output signal on line 6 is up and the clock signal on line 1 is down, FETs 8 and 9 conduct simultaneously and function as a voltage divider, so that the signal level on line 4 is raised to only a fraction of the value of the up data signal on line 2. FET 5 remains cut off and the output signal on line 6 remains high.

When the data and clock signals are both up, line 4 is up and output line 6 is down. The down signal on line 6 cu...