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Fabricating Complimentary MOS Transistors

IP.com Disclosure Number: IPCOM000078065D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Magdo, IE: AUTHOR [+2]

Abstract

This method can be used to fabricate complementary transistors having mixed crystal structure, by techniques compatible with recessed oxidation isolation.

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Fabricating Complimentary MOS Transistors

This method can be used to fabricate complementary transistors having mixed crystal structure, by techniques compatible with recessed oxidation isolation.

In this method the monocrystalline silicon substrate 10 is oxidized forming SiO(2) layer 12. A layer 13 of Si(3) N(4) is deposited and window 14 opened. Diffusion 16 is made and a second opening 17 is made for the P-channel device. An N-doped epitaxial Si layer 18 is deposited on the surface of body 10. N- doped single-crystal region 18 forms over window 17. In window 14, the P-type impurity diffuses upwardly in the single-crystal region forming region 20. Polycrystalline silicon 22 is formed over regions covered by the Si(3) N(4) layer
13. The overlying Si layer is thermally oxidized forming the layer 24 and a layer 26 of Si(3) N(4) deposited thereon. Annular openings 28 are formed through the layers 24 and 26 about each of the single-crystal regions 18 and 20, and a portion of the layer 22 removed forming groves 29. The body is then thermally oxidized forming SiO(2) isolation regions 30. Diffusion windows for forming source and drain are made through layers 24 and 26, P-type diffusions are made forming N-channel device 32. Similarly N-type impurity diffusions are made forming a P-channel device 34. The active parts of each of the metal-oxide semiconductor (MOS) devices are formed in single-crystal silicon, while the inactive parts extends into polycrystalline silicon...