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Browse Prior Art Database

Negative Resistance Using FET's

IP.com Disclosure Number: IPCOM000078067D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Gruodis, AJ: AUTHOR

Abstract

The circuit shown in Fig. 1 can be used to produce a negative resistance characteristic, as shown in Fig. 2. To achieve this characteristic the devices have the following properties (assuming N-channel devices): FET Width/Length Ratio Threshold Voltage T1 small VT1 < 0 T2 small VT2 > 0 T3 large VT3 < 0.

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Negative Resistance Using FET's

The circuit shown in Fig. 1 can be used to produce a negative resistance characteristic, as shown in Fig. 2. To achieve this characteristic the devices have the following properties (assuming N-channel devices): FET Width/Length Ratio Threshold Voltage

T1 small VT1 < 0

T2 small VT2 > 0

T3 large VT3 < 0.

The substrate of all devices is tied to a fixed potential. By reversal of all voltage polarities P-channel devices could be used.

The circuit operates as foIlows: With small voltage (Vx) across the circuit, T1 and T3 are on and T2 is off. Since T2 is off, current flows only through T3. As the voltage increases, the gate to source bias of T3 increases turning it on harder. Thus, the rate of change or current keeps increasing. This continues until VT2 is reached. At this point current starts to flow through T1 and T2. Further increases in voltage turns T2 on harder, until it requires more current than T1 can supply. This forces the gate voltage of T3 to drop, decreasing the total circuit current. As the voltage is increased beyond this point, the changes in substrate bias become evident (change of VT3 and VT1) and the current starts to increase again.

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