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Diffused Isolation and Etched Isolation Structure

IP.com Disclosure Number: IPCOM000078068D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Baker, TH: AUTHOR [+2]

Abstract

In order to obtain the highest adjustable value of capacitance for a given epitaxial isolation bed, a P+ diffused region is formed under another P-type region. The latter region is formed by a diffusion step used to form base regions for transistors at other locations on the chip.

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Diffused Isolation and Etched Isolation Structure

In order to obtain the highest adjustable value of capacitance for a given epitaxial isolation bed, a P+ diffused region is formed under another P-type region. The latter region is formed by a diffusion step used to form base regions for transistors at other locations on the chip.

Firstly, P+ regions 1 and 2 are diffused over the N-type substrate. Thereafter, an N-type, epitaxial region 3 is formed over the substrate. Next, a P-type, base region 4 is formed in the epitaxial layer 3. Then, oxide is removed in order to form recessed oxide isolation regions 6 and 7, for connecting to the pair of P+ diffused isolation regions 1. An epitaxial contact for the programmable or adjustable capacitor is shown at 8.

The P+ diffused region 2 joins with the base region 4 and thus incorporates the collector-isolation capacitance with the adjustable or programmable collector- base capacitance.

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