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Fabricating Submicrometer Silicon Devices

IP.com Disclosure Number: IPCOM000078099D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Bassous, E: AUTHOR

Abstract

It is well known that one of the ways to improve the performance and lower the cost of silicon devices and integrated circuits, is to reduce the size of the active elements and increase their density on a substrate of given area.

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Fabricating Submicrometer Silicon Devices

It is well known that one of the ways to improve the performance and lower the cost of silicon devices and integrated circuits, is to reduce the size of the active elements and increase their density on a substrate of given area.

A process is described herein which decreases the physical dimensions of the gate region of silicon devices and silicon integrated circuits, using conventional photolithography. In conventional photolithography, the minimum line width attainable is about 2 Micron due to limitations of optical systems. Smaller widths can be obtained by using electron-beam lithography and projection printing, but these methods are more complicated and more expensive than photolithography.

In field-effect transistor (FET) structures in which the gate region consists of a silicon film on top of a dielectric, the width of the gate can be reduced by thermally oxidizing the polycrystalline silicon (poly Si) followed by etching of the oxide formed on the poly Si. When silicon is oxidized to SiO(2), the thickness of the oxide formed is about twice the thickness of the reacted silicon. (More exactly, 1 Angstrom Si -> 2.17 Angstroms SiO(2)). Thus, a poly Si film when oxidized to yield an SiO(2) film 1 Micron thick, results in a reduction of the original poly Si film thickness by 0.46 Micron. In the case of a poly Si line similar to a gate in an FET, the thickness and the width of the line are decreased by an amount which is proportional to the thermally grown SiO(2) film. For, example, a poly Si line 2 Microns wide and 1.0 Micron thick when thermally oxidized produces an SiO(2) film 1 Mu thick. The poly Si line is now reduced to a line approximately 1 Micron wide and 0.5 Microns thick.

This approach can easily be applied to fabricate FET-type devices with self- aligned gate structures, in which the gate width is in the micrometer or submicrometer range.

The following procedure illustrates how a field-effect transistor with a poly Si gate 1 Micron wide is fabricated. The physical dimensions are given to help clarify the procedure. (See Fig. 1) 1) Silicon wafer is thermally oxidized (2500 Angstroms SiO(2)). 2) The oxide is etched from the device area by photolithography. 3) Thermal oxide is grown in the device area (150 Angstroms SiO(2). 4) Silicon nitride is deposited (150 Angstroms Si(3)N(4). 5) Polycrystalline silicon is deposited (1.3 Microns Si). 6) Poly Si is thermally oxidized (700 Angstroms SiO(2)). 7) Poly Si gate is delineated by photolithography. 8) The poly Si gate is thermally oxidized to form 1 Micron SiO(2). 9) Etch off 1 Micron SiO(2) on poly Si gate.
10) Silicon nitride is etched off.
11) Etch off 150 Angstroms SiO(2) in source and drain regions.
12) Diffuse N-type (or P-type) dopant in source...