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Utilization of Defective Memory Chips by Substituting Redundant Words for Defective Words

IP.com Disclosure Number: IPCOM000078119D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Beausoleil, WF: AUTHOR

Abstract

This is a monolithic memory made up of memory chips which have an additional redundant word on each chip. The chips are sorted and placed in memory locations, in accordance with the location of the defective word on each chip. The redundant word is selected dependent upon the chip position in the memory; that is, whenever the chip row address equals the word address. Since the chips are physically located in accordance it with the redundant word during address selection.

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Utilization of Defective Memory Chips by Substituting Redundant Words for Defective Words

This is a monolithic memory made up of memory chips which have an additional redundant word on each chip. The chips are sorted and placed in memory locations, in accordance with the location of the defective word on each chip. The redundant word is selected dependent upon the chip position in the memory; that is, whenever the chip row address equals the word address. Since the chips are physically located in accordance it with the redundant word during address selection.

The memory is shown in Fig. 1. Sixteen-address bits 0-15 are brought into each array card 10. The card 10 is made up of modules 16 on which are placed chips 18 (shown more fully in Fig. 2).

The address lines B0-B15 are split into eight lines 20 for word and bit decoding; four lines 22 and four lines 26 for chip select decoding by Y decoder 24 and X decoder 28, respectively. As a result of chip select decoding, one of sixteen lines Y(0)-Y(15) is energized and one of sixteen lines X(0)-X(15) is energized, to select the chin 18 at the intersection thereof.

Each chip has 18 has sixteen-word rows on it. The chins are sorted sixteen ways and placed on the card depending upon the location of the word containing a bad bit.

A compare circuit 23 is provided which compares the word address lines 21 with the chip row address lines 22. Whenever the two are equal, the "select redundant cells" line 25 is energized.

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