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General Purpose Monolithic Memory Linearizer

IP.com Disclosure Number: IPCOM000078122D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Soychak, FJ: AUTHOR [+2]

Abstract

This special purpose circuitry enables a nonlinear output from a nonlinear transducer 10 to be linearized in accordance with information stored in memory array 12, without tying up a general purpose system for this purpose. The output of a nonlinear transducer is typically differentially sensed and may be converted to a ground based system, if desired, in converter 14 connected to transducer 10 by lines 16 and 18. An analog-to-digital converter 20 is connected to converter 14 by line 22, and creates an address which is used to look up or address a correction word in the memory automatically, by use of address store and level set 24, connected to A/D converter 20 by lines 26. Address store and level set 24 is connected to memory array 12 by lines 28.

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General Purpose Monolithic Memory Linearizer

This special purpose circuitry enables a nonlinear output from a nonlinear transducer 10 to be linearized in accordance with information stored in memory array 12, without tying up a general purpose system for this purpose. The output of a nonlinear transducer is typically differentially sensed and may be converted to a ground based system, if desired, in converter 14 connected to transducer 10 by lines 16 and 18. An analog-to-digital converter 20 is connected to converter 14 by line 22, and creates an address which is used to look up or address a correction word in the memory automatically, by use of address store and level set 24, connected to A/D converter 20 by lines 26. Address store and level set 24 is connected to memory array 12 by lines 28.

Clock 30 is connected to A/D converter 20 by line 32 for providing required pulse beats for its operation. Clock 30 is also connected to memory drive circuits 34 by line 36, to provide pulses for their operation in the usual manner. Memory drive circuits 34 are connected to memory array 12 by lines 38. Lines 40 connect memory array 12 to sense amplifier 42. Output lines 44 of sense amplifier 42 are connected to digital-to-analog converter 46, the output of which forms one input to alumino circuit 48 on line 50. The other input of summing circuit 48 is connected to the output of converter 14 by line 52. Output 54 of summing circuit 48 may be connected to an A/D converter 56 by line 58, if it is desired to digitize the resulting linearized output.

In operation, A/D conv...