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Two Phase MOSFET Static Shift Register Employing Feedback Stage Resetting

IP.com Disclosure Number: IPCOM000078140D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Fisher, DE: AUTHOR

Abstract

A shift register, compatible with metal-oxide semiconductor field-effect transistor (MOSFET) devices, has been devised which employs two bistable "set-reset" latches per stage. A stage contains an upper register and a lower register with each register containing seven FET's, one FET for data input and the other six for the set-reset latching.

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Two Phase MOSFET Static Shift Register Employing Feedback Stage Resetting

A shift register, compatible with metal-oxide semiconductor field-effect transistor (MOSFET) devices, has been devised which employs two bistable "set- reset" latches per stage. A stage contains an upper register and a lower register with each register containing seven FET's, one FET for data input and the other six for the set-reset latching.

Fig. 1 shows the shift register and its two pulse phases and Fig. 2 is a timing chart for such two-phase shift register. When phase 1 (Phi 1) is up and a "1" appears as data, such data is transmitted to the set input FET of the lower register. The 1 occurring at the set input causes a 1 to appear at the output (point B of Fig. 1) of the lower register. Point A goes down in voltage as point B goes up in voltage, storing a 1 as the input of the upper register.

When Phi 2 is up, the 1 at point P is transmitted to the set-input of the upper register and the 1 appearing at Q causes a 1 to appear at the output D of the upper register, which 1 output couples back to the reset input of the lower register, causing a 0 voltage level at point B. Thus, the very data being shifted acts as a source of reset pulses for the shift register.

It has been found that the above-described shift register provides a reliable information shift register and storage register with large power supply variation tolerance, no minimum shift requirements, and requires considerably les...