Browse Prior Art Database

Regeneration Management in Volatile Capacitive Stores

IP.com Disclosure Number: IPCOM000078141D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Beausoleil, WF: AUTHOR [+2]

Abstract

This scheme regenerates AC stable cells or volatile storage cells in the backing store of a hierarchical memory, with a minimum of interference with the use of the memory by the system.

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Regeneration Management in Volatile Capacitive Stores

This scheme regenerates AC stable cells or volatile storage cells in the backing store of a hierarchical memory, with a minimum of interference with the use of the memory by the system.

Very dense memories can be made of semiconductive storage cells that need periodic data regeneration to retain their information. Storage cells of this type are referred to as AC stable cells. In a typical array design, one-half of all memory time must be apportioned to regeneration of such AC stable cells (even though as many as eight use cycles may be taken before a regen cycle). Because it is necessary to allot memory time to regenerate AC stable cells, the apparent access time of the cells is increased and this increase offsets some of the advantage in density of AC stable cells. It is suggested that, to a great extent, regeneration cycles may be masked to provide higher speed operation.

In a hierarchical memory, normally fewer than 50% of the memory cycles of the backing store will be required for accessing. Furthermore, the backing store may be divided into quarters or eighths, each with its own accessing and regeneration circuitry so that less than 12 1/2% of all cycles in any eighth is needed for system access.

With less than 30% of the cycles needed for system access, regeneration can be easily controlled by two counters 10 and 12. A binary counter 12 contains the addresses of the next group of pages in the memory to b...