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Browse Prior Art Database

Optimization of Light Emitting Diode Chip Design

IP.com Disclosure Number: IPCOM000078165D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Elliott, JC: AUTHOR

Abstract

Monolithic light-emitting diode chip arrays are optimized by significantly reducing chip drive lines about 45%, as well as reducing support logic through character multiplying, and effecting an improved font with respect to the majority of characters.

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Optimization of Light Emitting Diode Chip Design

Monolithic light-emitting diode chip arrays are optimized by significantly reducing chip drive lines about 45%, as well as reducing support logic through character multiplying, and effecting an improved font with respect to the majority of characters.

Examination of diode combinations utilized in making standard ASCII characters, reveals that certain combinations are always coincident. Therefore, by interconnecting coincident diodes on the chip, drive lines are reduced. Eleven combinations of two or more existing coincident diodes were found to reduce the number of drive lines from 35 to 19, on a 5 x 7 array.

The following method accomplishes coincident diode combination interconnection: (a) characters are laid out on grid paper using the desired font and chip array, (b) coincident groups between characters are arranged in subgroups, (c) conflicting character groups, if any, are isolated until all groups have been surveyed, (d) alternative character fonts are utilized for conflicting groups and, if necessary, subgroups established, therefore subgroups and individual diodes form a new chip layout, and (e) diodes in each subgroup are interconnected.

The drawing illustrates an optimized monolithic 5 x 7 light-emitting diode chip array having 19 drive lines.

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