Browse Prior Art Database

Testing Defective Serial Shift Register

IP.com Disclosure Number: IPCOM000078171D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

A technique is described for testing defective shift registers for large-scale integrated (LSI) chip design and reliability studies. The technique reveals the locations of weak storage nodes or the last stuck bit in the circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Testing Defective Serial Shift Register

A technique is described for testing defective shift registers for large-scale integrated (LSI) chip design and reliability studies. The technique reveals the locations of weak storage nodes or the last stuck bit in the circuit.

Many serial shift register circuits can be cleared and preset with '1' (or '0') in every internal bit by means other than using the input terminal, thereby bypassing the defective bits. Fig. 1 represents two cases of such a preset 16-bit shift register having two bad bits at Nos. 9 and 14, counted from the output terminal. The bad cells or the cells next to the bad ones toward the output terminal (Nos. 8 and 13), also may appear to have stuck 0's or stuck 1's. If bad bit No. 9 causes the next one (No. 8) to have a stuck 0, the shifted output waveform for case one will comprise seven 1's followed by all 0's. For a stuck 1 defect, the shifted output waveform for case two will comprise seven 0's followed by all 1's. Thus, one can discover that bit No. 8 from the output terminal is a stuck bit. The other bad bit (No. 14) and stuck bit (No. 13) are masked by bad bit No. 9 and cannot be discovered.

It is also possible that the shift register shown in Fig. 1 is a dynamic one and has, for example, defective bits Nos. 5, 11, and 14, which cannot hold information (charge) long enough for low-frequency operation. After the clear- and-preset operation with 1 (or 0) in every bit, the register is held under this condition for a controllable amount of time (corresponding to the failure frequency) before shifting the inform...