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Shift Control for Shift Register

IP.com Disclosure Number: IPCOM000078172D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Jessep, DC: AUTHOR [+3]

Abstract

Multiphase clocking is employed to accomplish shift control among a set of shift register latch cells, coupled together in a shift register to perform a scan-in/scan-out operation.

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Shift Control for Shift Register

Multiphase clocking is employed to accomplish shift control among a set of shift register latch cells, coupled together in a shift register to perform a scan- in/scan-out operation.

A set of latch circuits 1-4 is coupled in sequence as cells of a shift register' A scan input is provided at 5 to cell 1 and a scan output derived at 6 from the last latch cell of the register. The input at 5 and the output at 6 are independent of the normal data and clock inputs for each of the latches 1-4 and the output derived from each of these latches.

In shifting the input at 5 through the cells of the shift register in sequence, a shift clock control is obtained by using a single-delay modulated clock. The basic shift clock signal is provided at 7 and is delayed through delay circuit 8 and inverter 9, to be gated against itself at 10 to provide a short duration clock pulse. This short duration clock pulse appears at A and is coupled to the last cell 4 of the shift register. Successive delays are imparted to this basic clock pulse by delay circuits 11, 12 and 13 to provide the clock pulses B, C and D, respectively. These clock pulses are applied, respectively, to the cells, 3, 2, and 1.

The duration of the clock pulses must be long enough to assure proper setting of the latch circuits. The clock pulses must also be separated to assure operation of the shift register. To obtain the desired duration and separation, the values N1 and N2 of the delay...