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Bipolar Field Effect Transistor Voltage Conversion Driver

IP.com Disclosure Number: IPCOM000078183D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Hansen, AA: AUTHOR [+2]

Abstract

(FET) memory array circuits, requires that the relatively lower bipolar voltage levels be converted to the relatively higher FET voltage levels. The described conversion driver accomplishes the voltage level conversion without requiring "off chip" high-voltage high-power interface drivers, and is suitable for integration with FET memory array circuits on the same chip.

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Bipolar Field Effect Transistor Voltage Conversion Driver

(FET) memory array circuits, requires that the relatively lower bipolar voltage levels be converted to the relatively higher FET voltage levels. The described conversion driver accomplishes the voltage level conversion without requiring "off chip" high-voltage high-power interface drivers, and is suitable for integration with FET memory array circuits on the same chip.

When the restore pulse of Fig. 2 rises to the V2 level, transistor T3 of Fig. 1 turns "on", charging node N1 to a voltage within a threshold drop of the V2 level. Since the chip-select voltage is at ground potential, node V 0UT is held at ground potential. Voltage P.G. also is less of the SAR input voltage level. Node N2 is also charged to the potential at node N1 through isolating transistor T2 which is turned on. When the restore pulse falls back to ground potential, both nodes N1 and N2 remain charged to a potential equal to V2 minus the threshold voltage drop V.

If one or more SAR inputs are at ground potential when the P.G. pulse turns on, nodes N1 and N2 will discharge. Then the P.G. pulse is turned off and the chip-select pulse is turned on. Since node N1 is discharged, transistor T4 remains off and the potential V OUT remains at zero volts.

If all SAR inputs are at voltage V1, transistor T1 remains off when the P.G. pulse turns on. Consequently, nodes N1 and N2 remain charged to V2 minus V threshold. When the chip select pulse turns...