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Synchronous Detector for Monopulse Key Sampling Electronic Keyboard

IP.com Disclosure Number: IPCOM000078184D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Fisher, DE: AUTHOR [+2]

Abstract

The figure shows a synchronous detector for monopulse key sampling electronic keyboards.

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Synchronous Detector for Monopulse Key Sampling Electronic Keyboard

The figure shows a synchronous detector for monopulse key sampling electronic keyboards.

Clock pulses on input lines 3 and 13 are transmitted to triggered gate 1, responsive at its input to produce signal indications at output B if capacitive key 5 is in an undepressed condition, and to produce another signal at output A if key 5 is depressed. With key 5 in its depressed state, clock pulses are passed to input 13 of triggered gate 1 and the leading edge of the first pulse on output A of gate 1 resets level generator 9, whereby the levels at output C and D of level generator change. The change on output C acts to reset single-pulse gate 15.

Since output A from gate 1 is coupled directly to input 19 of single-pulse gate 15, the first clock pulse thereon, which reset level generator 9, arrives at input 19 of gate 15 simultaneously with the resetting thereof, in level change at input 17. Thus, the first clockpulse to arrive upon depressing of key 5 is passed through gate 15 with its trailing edge acting to reset the gate, whereby a single-output pulse E in synchronism with the system clock is produced.

Output D from level generator 9 is fed back to the input 13 of triggered gate 1 via variable-threshold feedback network 11, which changes the trigger level on gate 1 in accordance with the voltage output level at the output D. This prevents key bounce and the like in the capacitively coupled clock puls...