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Large Capacity Memories Using Nonreversible Memory Cells

IP.com Disclosure Number: IPCOM000078191D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR

Abstract

The number of write operations to which a memory cell in a large-capacity file store is subjected during the lifetime of the store is quite restricted. For instance, a file store with a capacity of N x 10/9/ bits organized in N memory planes may have a uniform distribution of write operations among all memory cells, such that the total number of write operations per memory cell is about 500. This factor can be utilized by constructing large-capacity memories using memory cells which are not truly reversible. Two classes of devices can be used: those which can be switched reversibly for a limited number of switching operations and those which can be degraded irreversibly. Several bistable resistor devices belong to the first class of devices.

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Large Capacity Memories Using Nonreversible Memory Cells

The number of write operations to which a memory cell in a large-capacity file store is subjected during the lifetime of the store is quite restricted. For instance, a file store with a capacity of N x 10/9/ bits organized in N memory planes may have a uniform distribution of write operations among all memory cells, such that the total number of write operations per memory cell is about 500. This factor can be utilized by constructing large-capacity memories using memory cells which are not truly reversible. Two classes of devices can be used: those which can be switched reversibly for a limited number of switching operations and those which can be degraded irreversibly. Several bistable resistor devices belong to the first class of devices.

As an example of memory cell materials for the second class of devices, phosphorous materials used in TV screens emit photons when irradiated by electrons, and lose efficiency of photon emission as a function of the accumulated electron charge. Hence, the memory plane 10 can comprise a plurality of pairs of adjacent phosphor spots 12A,12B, as in the figure. The binary value 1 can be assigned to the high-efficiency spot and a binary 0 to the low-efficiency spot. Of course, these values can be assigned to the right or left spots rather than in accordance with the efficiencies of each.

For reading information from memory plane 10, an electron beam is deflected by a DC signal to the center of the area between the spots. A small AC voltage of proper amplitude is superimposed on the DC signal and causes the beam to oscillate between the left and right-hand spots 12A and 1...