Browse Prior Art Database

Single Electrode One Device Cell

IP.com Disclosure Number: IPCOM000078204D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Spampinato, DP: AUTHOR [+2]

Abstract

A memory cell of the charge-coupled type is shown in the figure. The structure comprises a substrate 1 of semiconductor material such as silicon of an appropriate conductivity type, N-type, for example. Diffusions 2 of opposite conductivity type are formed in substrate 1 and act as bit lines in an array of the devices being described. Extending from each of the diffusions 2, is an ion implanted region 3 of the same conductivity type as substrate 1 but of higher doping level. A storage area 4 is provided beneath a thin oxide region 5. A thick oxide region 6 is disposed in overlying relationship with bit line diffusions 2.

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Single Electrode One Device Cell

A memory cell of the charge-coupled type is shown in the figure. The structure comprises a substrate 1 of semiconductor material such as silicon of an appropriate conductivity type, N-type, for example. Diffusions 2 of opposite conductivity type are formed in substrate 1 and act as bit lines in an array of the devices being described. Extending from each of the diffusions 2, is an ion implanted region 3 of the same conductivity type as substrate 1 but of higher doping level. A storage area 4 is provided beneath a thin oxide region 5. A thick oxide region 6 is disposed in overlying relationship with bit line diffusions 2. Adjacent each bit line diffusion is a "dump" gate 7 which is formed of polysilicon having an oxidized surface portion 8, which insulates the conductive polysilicon gate 7 from an overlying metal word line 9.

The above-described structure has two main features: 1) A channel area which is ion implanted; 2) An additional gate called the "dump" gate 7 between the storage area 4 and the bit line 2 of the adjacent cell.

Ion implantation region 3 can be kept very thin at the surface of substrate 1, enabling a threshold enhancement in the device area, but without appreciable increase in the bit line capacitance. In keeping the ion implanted area very thin, the substrate characteristics of the metal-oxide semiconductor field-effect transistor (MOSFET) gating device are not substantially altered.

The use of "dump" gate 7 pe...