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Bubble Domain Random Access Memory Having Multilevel Decoding

IP.com Disclosure Number: IPCOM000078207D
Original Publication Date: 1972-Nov-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Chang, H: AUTHOR

Abstract

This random-access memory uses multilevel decoding to reduce the number of interconnections needed for access of information. A single-sense line per chip and time sharing of a sense line by many chips is also used, resulting in a minimum number of sense lines.

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Bubble Domain Random Access Memory Having Multilevel Decoding

This random-access memory uses multilevel decoding to reduce the number of interconnections needed for access of information. A single-sense line per chip and time sharing of a sense line by many chips is also used, resulting in a minimum number of sense lines.

Referring to Fig. 1, the magnetic sheet 10 in which bubble domains exist is divided into chips 12 by two sets of strip lines, designated X bands 14 and Y bands 16. These bands are wide strip lines which supply a magnetic field to an entire strip of the magnetic sheet. A chin is defined as the overlapping area of one X-band and one Y-band.

Finer x lines and y lines are used to define memory cells.

These x and y lines meander through the entire memory plane. In Fig. 2, each x and y line represents a group of lines as shown in more detail in Fig. 3. In Fig. 3, there are x lines x(1), x(2), x(3), ... intersecting with y lines labeled 0, 1, R, and S. The intersection of groups of these lines defines a memory cell A, B, ... F, such as that shown in dashed lines designated A. The 0, 1, and R lines are conductors, while the S lines are permalloy strips used for sensing domains. Activation of selected x and y lines causes bubble domains BD to move to positions designating a 0 bit, and a 1 bit. When the domains are moved to a position adjacent the sense lines, they will induce a voltage change in these lines which is detected. As shown in memory cell E, an expansion operation will cause the domain BD to expand before sensing. Located on the 1 and R lines are permalloy dots 18 which are used to trap domains in order to split them. One of the split domains is moved to a position adjacent the S line for sensing.

The memory is bit organized, having N bits in a word distributed among N different chips. The number of bits in a chip is also the number of words. To operate a memory cell, an appropriate x line and y line is activated, as well as an X band and a Y band in order to select a bit for read or write operation. The activation of the x line and y line tends to act on a bit in each chip, while the a...