Browse Prior Art Database

Digital To Analog Converter

IP.com Disclosure Number: IPCOM000078222D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Croisier, A: AUTHOR

Abstract

This description relates to a very simple converter for recovering a signal in the analog form from its representation in PCM form.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Digital To Analog Converter

This description relates to a very simple converter for recovering a signal in the analog form from its representation in PCM form.

The figure is a diagrammatic showing of the converter and a timing diagram for the control signals. The converter consists of a shift register 1, the number of positions of which corresponds to the number of bits in a PCM character, and of an AND circuit 2 whose output signal 3 controls a switch S1 located between a current source 4 and an integrator 5, whose output signal is applied to a capacitor C2 through a switch S3. Integrator 5 which, in this example, consists of an operational amplifier 6 and a capacitor C1, includes a switch S2 allowing resetting of capacitor C1. AND circuit 2 receives the 0N output of the shift register 1, a gate signal G and a strobe signal STR. Switches S1, S2, S3 are, respectively, controlled by signal on 3, and by two control signals CS2, CS3.

When the converter is operating, switch S1 controls a current I generated by current source 4, which is integrated in capacitor C1, switch S2 resets the integrator, and switch S3 samples the integrated voltage and stores it in capacitor C2 according to the timing diagram.

Prior to time t=0, the data are entered into shift register 1 through a burst of clock pulses CL, and switch S2 is closed for a short-time interval in order to reset integrator 5.

Conversion begins at time T as the gate signal G is raised. Current I is or is not integrated for a period of time T (between instants T and 2T), depending upon the value A1 of the first data bit. At time 2T, shift register 1 is advanced by a new clock pulse and current I is or is not integrated for a period of time 2T (between instants 2T and 4T), depending upon the value A2 of the second data bit. At time 4T, current I is...