Browse Prior Art Database

Avoidance of Refresh Times in Dynamic Memories

IP.com Disclosure Number: IPCOM000078226D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 4 page(s) / 34K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

By their nature, dynamic memory cells must be periodically refreshed in order to avoid loss of the stored information. At present, refreshing is done either by splitting the memory cycle into two subcycles, with a normal read/write operation during one subcycle, and a sequential restore of memory words during the other, or by restoring in the burst mode, in which the memory is operated normally until restoring is needed, whereupon read/write activity is stopped, and the information is restored.

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Avoidance of Refresh Times in Dynamic Memories

By their nature, dynamic memory cells must be periodically refreshed in order to avoid loss of the stored information. At present, refreshing is done either by splitting the memory cycle into two subcycles, with a normal read/write operation during one subcycle, and a sequential restore of memory words during the other, or by restoring in the burst mode, in which the memory is operated normally until restoring is needed, whereupon read/write activity is stopped, and the information is restored.

The split-cycle approach is undesirable, since it results in lengthening the memory cycle by approximately a factor of 2. The burst mode works well with dynamic memory cells such as a four-device cell which can be restored without an external sense amplifier, thus permitting the whole memory to be restored in parallel. The burst mode is less attractive with cells like the one-device cell and charge-coupled device cells, where the sense amplifier and bit line are needed for restoring information. This allows only 1 bit to be restored on a sense amplifier at a time, and the more bits put on a sense amplifier, the larger the time spent in restoring, which can become undesirably large.

In the present approach, the restore cycles are buried under the normal read/write cycles, and are hardly ever seen. Assume that the memory system is broken up into a number of subarrays, each having N words, M-sense lines, and M-sense amplifiers, one for each sense line in the subarray (Thus, there are N bits on each sense amplifier). These subarrays may be fabricated with one or more per chip, however, the chips are bit organized (i.e., only 1 bit per chip is gated out at a time).

Now consider what happens in the prior art when an address is sent to the memory. (Only a 1-bit memory word will be considered here, but the extension to the usual 64-bit or other length word is obvious). The address bits are used to select a word line, a bit line, and to decode a "chip select" to select between subarrays, and the cell is read or written. Since, in the 1-device cell, turning on the word line destroys the information on the cell, all cells along the selected word line in the subarray must be read out and written back in -- in other words, they are refreshed. In the present approach, the corresponding word line is selected in every subarray, and the information is restored along one word line in every subarray simultaneously. A single selected bit is read or written to the outside world; all other bits are restored, and, in effect, one word line is restored in each subarray.

In this manner, the restore cycle is done in parallel with the normal operating cycle, and does not consume additional time. No time is needed for the restore cycle if during about one-half the information retention time, all the word lines are refreshed (the factor of one-half is necessary because a word line refreshed at the beginning of a retention p...