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Browse Prior Art Database

Fast Flow Through Flip Flop

IP.com Disclosure Number: IPCOM000078236D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Fisk, DE: AUTHOR

Abstract

A circuit is provided that decreases the time required for data to propagate through a register, by using a two-way AND-OR circuit in conjunction with the usual D-type flip-flop.

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Fast Flow Through Flip Flop

A circuit is provided that decreases the time required for data to propagate through a register, by using a two-way AND-OR circuit in conjunction with the usual D-type flip-flop.

To describe the circuit in greater detail, a flip-flop circuit 11 receives inputs from a data source 13 and a clock 15, with its sole output being fed to a first AND circuit 17 that has its other input connected via an inverter 19 to the clock 15. A second AND circuit 21 has one input connected directly to the data source 13 and the other connected to the clock 15. The outputs of both of the AND circuits 17, 21 are connected to an OR circuit 23.

With this circuit, when data is clocked into the flip-flop 11, the data output line 25 shows the data input length 13; and when the clock line goes down, the data output 25 shows the flip-flop contents.

The two-way AND-OR circuit at the data output is much faster than the D- type flip-flop. Accordingly, a decrease in propagate time is achieved, which enables the register flip-flops to be optimized for power dissipation and other normally secondary requirements.

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