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Browse Prior Art Database

Automatic Margin Indexing for Printers

IP.com Disclosure Number: IPCOM000078251D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Halich, VV: AUTHOR [+3]

Abstract

Automatic margin indexing is provided by shifting the print line data in the Printer Control Unit, at the time of data transfer from a computer to the printer. The number of positions for the shift and the direction of the shift are provided in a specially coded additional data byte during the FCB (Forms Control Buffer) Load Command.

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Automatic Margin Indexing for Printers

Automatic margin indexing is provided by shifting the print line data in the Printer Control Unit, at the time of data transfer from a computer to the printer. The number of positions for the shift and the direction of the shift are provided in a specially coded additional data byte during the FCB (Forms Control Buffer) Load Command.

For example, since the usual FCB data uses only Bus Out bit 3 through Bus Out bit 7, the additional FCB byte referred to as the Index Byte can be transferred as the first FCB data byte, coded as shown in Fig. 1, using the presence of the 0 bit to indicate a margin index shift to the right, and the presence of a 1 bit a margin index shift to the left. Hence, by examining the first FCB byte during FCB load, it can be determined if automatic margin indexing is required for the forms during printing.

The logic for loading indexing information is shown in Fig. 2. During the first clock cycle the code of the data byte determines whether a right or left shift is required, through ANDs 10 and 12 which control Index Right Latch 14 and Index Left Latch 16, respectively. Index Byte Latch 18 is set through OR 20 if either Index Right or Index Left Latch is set. Index Byte Latch 18 is used to stop the FCB write operation during that clock cycle and prevent the FCB Address Ring from advancing for the next clock cycle. At the time the Index Byte Latch is set, a Set Index Byte signal gates the remaining Bus Out Bits 2 through 7 and stores the index data count in Index Data Latches 22.

The Index Data Latches information is put through Decode Translate Logic 26 to come out on modified binary Decode Address Lines 1, 2, 4, 8, 13, 25, and 50, which correspond to the Print Line Buffer Address Trigger values. Compare Logic 28 gating is used to generate the Index and PLB Address Compare, when the Decode Address Lines 30 and the PLB Address Triggers 32 have the same binary value.

Once the Index Right or Index Left Latch is set, it is not reset until the next time a FCB Load signal is generated and applied through OR 34. The Index Byte Latch 18 is reset during the next clock cycle Time R1 through AND 35 and OR 36. Except for the first byte of FCB Load, the remaining FCB bytes are treated in the normal fashion.

The logic for, and a schematic illustration of an Index Right operation are shown in Figs. 3 and 4. At the start of the Write Command, the Index Right Preset Address signal is generated at AND 40 in Fig. 3. In conjunction with Decode Address Lines through Gating Logic 42, this produces the proper DC set and reset signals for the appropriate PLB Address Triggers in Fig. 2. These triggers would, for example, be set to the bi...