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Memory Circuits Power Gating Scheme

IP.com Disclosure Number: IPCOM000078255D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Hockedy, R: AUTHOR

Abstract

In pulse powered integrated memory circuits a significant power saving advantage can be realized by depowering the circuits as soon as a zero is read, since power is not needed to maintain a read-zero cycle. Since over 80% of all memory operations are read operations and less than 10% are write operations, a read-zero operation occurs approximately 45% of the time. By depowering of the circuits as soon as a zero is read, power-up time can be reduced by approximately 15% which results in an improved duty cycle, a lowering average junction temperature and improved reliability.

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Memory Circuits Power Gating Scheme

In pulse powered integrated memory circuits a significant power saving advantage can be realized by depowering the circuits as soon as a zero is read, since power is not needed to maintain a read-zero cycle. Since over 80% of all memory operations are read operations and less than 10% are write operations, a read-zero operation occurs approximately 45% of the time. By depowering of the circuits as soon as a zero is read, power-up time can be reduced by approximately 15% which results in an improved duty cycle, a lowering average junction temperature and improved reliability.

The figure shows the circuit for accomplishing this result which comprises a sense amplifier and B+ pulsed powered voltage. This circuit uses a feedback mechanism to shut off the B+ voltage in a read-zero condition. The information;
i.e., either a read 1 or a read 0 comes from the bit lines B1 or B0 into the bases of transistors T1 and T2, respectively. Transistors T3 and T4, emitter coupled to the collectors of transistors T1 and T2, respectively, provide common-base stages to buffer the collectors of transistors T1 and T2. When a 1 is read, the base of transistor T1 is higher than the base of transistor T2. In this condition transistor T1 is on and a current flows thru the data out node. Simultaneously, transistor T2 is off and the base of T5 is high, which causes transistor T6 to turn on and supply B+ output voltage to the circuits connected to the emitt...