Browse Prior Art Database

Positive Polarity Bistable Resistor Read Mostly Memory

IP.com Disclosure Number: IPCOM000078258D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Selleck, JE: AUTHOR

Abstract

This is a memory system having the ability of selecting, erasing and writing with opposite plurality while using the same decode logic, thereby is applicable for random-access memories with a slow write cycle speed. This system uses a row decoder and a column decoder feeding an array, each decoder being switchable from an OR circuit to a NOR circuit so that positive pulses can be used to read, write and erase. The row decoder is biased to act as an OR circuit when the column decoder is biased to act as a NOR circuit, to write or to read. In order to erase, the row decoder is biased to act as a NOR circuit while the column decoder is biased to act as an OR circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Positive Polarity Bistable Resistor Read Mostly Memory

This is a memory system having the ability of selecting, erasing and writing with opposite plurality while using the same decode logic, thereby is applicable for random-access memories with a slow write cycle speed. This system uses a row decoder and a column decoder feeding an array, each decoder being switchable from an OR circuit to a NOR circuit so that positive pulses can be used to read, write and erase. The row decoder is biased to act as an OR circuit when the column decoder is biased to act as a NOR circuit, to write or to read. In order to erase, the row decoder is biased to act as a NOR circuit while the column decoder is biased to act as an OR circuit.

The system as shown in the figure, comprises a bistable resistor read-mostly array 10 coupled to a plurality of row drivers 11, a plurality of column drivers 12, and presense amplifiers 13. The row drivers 11 are connected to a row address signal source 14, thru an OR/NOR logic gate 15 and a true-complement generator 16. The column driver is connected to a column address line 17, thru an OR/NOR logic gate 18 and a true-complement generator 19. The presense amplifier 13 is connected to a final sense amplifier 20, which has a data I/O input line 21 and a read/write signal input line 22. Both OR and NOR logic gates 15 and 18 each have read, write and erase inputs.

The true-complement generators 16 and 19 and the final sense amplifier 20 are normal bipolar memory circuits. The OR/NOR logic gate is a NOR circuit under a first voltage condition, and an OR circuit under a second voltage condition. The drivers, both row and column, are used for three purposes: 1) the row drivers pulse the cell to read or to write a "1", while the column drivers pulse the cell to write a "0"; 2) the unselected column drivers during the read operation clamp the sense nodes, so only the selected presense amplifier is able to sense the signal and feed it to the common final sense amplifier, while unselected row drivers clamp the unselected word lines to minimize cross talk; 31 all selected drivers during the erase place the unselected cells in half or unselected conditions, whi...