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Emitter Coupled Logic Circuit

IP.com Disclosure Number: IPCOM000078288D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 45K

IBM

Related People

Betts, AJ: AUTHOR [+4]

Abstract

The figure shows a logic circuit which comprises three main parts. 1. Basic Logic Stage.

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Emitter Coupled Logic Circuit

The figure shows a logic circuit which comprises three main parts. 1. Basic Logic Stage.

Transistors T1, T2, T3 and resistor R1 constitute a two-input emitter-coupled logic element, the emitter current I being provided by the current source T4, R4. The logic UP level is Vx and the logic DOWN level is Vx - 1R1. 2. Current Defining Stage.

The current I for the logic element is defined by the current mirror components T10 to T14, R6 to RS, R10 and the supplies VP1 and VN2. The current defined is: I approx. = VN 2 - 2V(BE) + 2V(BE) = V(N2) over R7 + R8 and is thus substantially independent of variations in V(BE) for the transistors. 3. Supply Generator.

The supply generator components T5 to T9, R2, R3, R5 and R9 sample the defined current I, and establish a logic element supply voltage Vx equal to the logic reference potential VR [ IR2. The logic reference VR is generated off-chip and supplied in common to a number of chips. Since R2 ] R1 divided by 2: Vx = VR + 1R1/2. which is the UP logic level. The DOWN logic level is Vx - IR1 -- VR - 1R1/2.

Therefore, the logic swing is +/- 1R1/2 about VR. Since I is inversely proportioned to R7 + R8, the logic swing is proportional to R1/(R7 + R8). Thus the logic swing is dependent upon the ratio of resistors only and not on their absolute values, and a much better tolerance can be obtained.

Thus a well-defined swing relative to VR can be obtained. Furthermore, since VR is distributed in common to a...