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Doped P & N Pockets for Complementary FETs

IP.com Disclosure Number: IPCOM000078366D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Wu, LL: AUTHOR

Abstract

Shown are steps of a method for forming both P & N doped pockets in silicon, which can be used for fabrication of semiconductor devices such as complementary field-effect transistor (FET) devices; 1) Initial oxidation of a (111) N(or P) substrate 1 - see Fig. 1b; 2) Opening of a window 2 for a P (or N) pocket with the sides of the windows parallel to the AO or BO direction, see Fig. 1A; 3) Use of an isotropic etch to form about a pit 3 as shown in Fig. 2; 4) Stripping of the oxide layer; 5) Growth of a P (or N) epitaxial layer 4 in a thickness of about 4/mm, as shown in Fig. 3; 6) Reoxidation of the substrate to form the dielectric layer 5; 7) Opening of a window 6 for an N (or P) pocket as shown in Fig. 4; 8) Use of an isotropic etch to form about a 6/mm pit 7 as Shown in Fig.

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Doped P & N Pockets for Complementary FETs

Shown are steps of a method for forming both P & N doped pockets in silicon, which can be used for fabrication of semiconductor devices such as complementary field-effect transistor (FET) devices;
1) Initial oxidation of a (111) N(or P) substrate 1 - see Fig.

1b;
2) Opening of a window 2 for a P (or N) pocket with the sides of the windows parallel to the AO or BO direction, see Fig. 1A;
3) Use of an isotropic etch to form about a pit 3 as shown in

Fig. 2;
4) Stripping of the oxide layer;
5) Growth of a P (or N) epitaxial layer 4 in a thickness of about

4/mm, as shown in Fig. 3;
6) Reoxidation of the substrate to form the dielectric layer 5;
7) Opening of a window 6 for an N (or P) pocket as shown in Fig. 4;
8) Use of an isotropic etch to form about a 6/mm pit 7 as Shown

in Fig. 5;
9) Stripping of the oxide layer 5;
10) Use of an isotropic etch to smooth the topology as shown in Fig. 6.

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