Browse Prior Art Database

Low Power Gated FET Latch

IP.com Disclosure Number: IPCOM000078367D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Kraft, WR: AUTHOR [+2]

Abstract

This gated latch design eliminates power dissipation in the inverter pair T2, T3 after data has been written into the latch. This is accomplished by returning the gate line of load device T2 to the Data-in strobe line, which controls the gate of transfer device T1.

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Low Power Gated FET Latch

This gated latch design eliminates power dissipation in the inverter pair T2, T3 after data has been written into the latch. This is accomplished by returning the gate line of load device T2 to the Data-in strobe line, which controls the gate of transfer device T1.

When the Data-in strobe line is at a VDD level, data is entered into the cell, either T6 or T9 conducts and the Data and Data outputs become valid.

The outputs are then held by the cross-coupled device pairs T4, T7 and T5, T8. When the Data in strobe line returns to ground, device T2 can no longer conduct, resulting in no power dissipation in inverter pair T2, T3 until the next write cycle.

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