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Nonvolatile Read Mostly Memory Cell

IP.com Disclosure Number: IPCOM000078369D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Davidson, EE: AUTHOR [+4]

Abstract

This memory cell is adapted for fast reading of a floating-gate avalanche injection metal oxide semiconductor-(FAMOS) device. Reading speed is enhanced by the provision of a diode coupled precharge line and a bipolar emitter-follower for each FAMOS device cell.

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Nonvolatile Read Mostly Memory Cell

This memory cell is adapted for fast reading of a floating-gate avalanche injection metal oxide semiconductor-(FAMOS) device. Reading speed is enhanced by the provision of a diode coupled precharge line and a bipolar emitter-follower for each FAMOS device cell.

Diode D1 improves the discharge time for node A. By discharging node A on all of the cells at the beginning of a Read cycle, bipolar transistor T1 is held OFF to prevent any false flow of capacitive currents from any of the selected cells. Diode D1 does not shunt any base current from T1 during the selection, because it is back biased.

Since the FAMOS device Q1 automatically stores a 0 when fabricated or after an erasing operation, it is necessary to write into only those cells that should have a 1 stored in them. This is accomplished by lowering the bit line to approximately -35 volts and selecting (turning ON) Q2, as shown in the figure. The collector of T1 is left open during this operation to prevent any large currents due to transistor action.

Since T1 could contain some residual charge from a previous operation, the precharge line is lowered at the beginning of a Read to discharge node A. For a similar reason, the bit line is simultaneously discharged. If Q1 stores a 0, it behaves as an open circuit and T1 remains OFF when Q2 is selected. However, if Q1 stores a 1, then base current flows to T1 during the time Q2 is selected. T1 turns ON and very rapidly charges th...