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Clamped Output TTL Internal Circuit

IP.com Disclosure Number: IPCOM000078372D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Gopalakrishna, YR: AUTHOR

Abstract

The output level of the Transistor-Transistor logic (TTL) circuit for large-scale integration shown in the figure is clamped at the up level (logical "1"), reducing the swing up to the power supply voltage by a Schottky diode D3.

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Clamped Output TTL Internal Circuit

The output level of the Transistor-Transistor logic (TTL) circuit for large-scale integration shown in the figure is clamped at the up level (logical "1"), reducing the swing up to the power supply voltage by a Schottky diode D3.

Diodes D1, D2, D3 are Schottky Barrier diodes. D1 and D2 keep transistors T1 and T2 out of saturation. D3 clamps the up level of the output when transistor T2 is OFF.

The figure shows the internal circuits on the chip, one driving the other on the chip. When A, B, C, D inputs are all up, V(OUT) will be in down level voltage (logical "0") and transistor 2 of Driver is CW. V(DOWN) = (V(bb) + V(BE2) - V(D2)) The RECEIVER is OFF and the up level voltage V(UP) is given by: V(UP) = (V(DOWN)) + V(BE1) - V(D1) + V(D3) V(UP) = (V(bb) + V(BE2) - V(D2)) + V(BE1) - V(D1) + V(D3) A nominal example of the circuit voltage is V(bb) = -1.5 volts; V(BE2) = 0.85V; V(D2) = 0.58V, V(BET1) = 0.82V; V(D1) = 0.58V; V(D3) =
0.56V; and V(UP) = 0-.430 volt (clamped). The up level clamp could be adjusted by varying D3.

The above circuit works without D1 or D2 or both, with D3 clamping the up level.

The diode capacitance D3 is a very small percentage of the collector-base capacitance and hence, does not affect performance of the circuit.

Resistor R(L) could be adjusted to have a sufficient up level noise margin of the circuit and, in addition, decrease the loading effect on the driver.

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