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Fabricating Complementary Transistors

IP.com Disclosure Number: IPCOM000078378D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Magdo, I: AUTHOR [+2]

Abstract

This process can be used to fabricate complementary field-effect transistors.

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Fabricating Complementary Transistors

This process can be used to fabricate complementary field-effect transistors.

In the process, a thermal SiO(2) layer 10 is grown on a silicon substrate 12 embodying an N-type dopant. A layer 14 of silicon nitride is deposited over layer 10, and windows 16 and 18 formed therein. The exposed portions of SiO(2) layer 16 in window 18 are removed by etching and a P-type dopant diffused therein, forming diffused regions 20. Subsequently, the surface of substrate 12 is reoxidized and a relatively thick layer 22 of SiO(2) is sputter deposited or deposited by pyrolytic deposition. Windows 24, 26 and 27 are etched in layer 22 and subsequently filled in by selective epitaxial deposition, as shown in Fig. 4. As indicated in Fig. 3, p-type region 25 is optional. As indicated in Fig. 4, region 28 and region 30 are monocrystalline, whereas region 32 is polycrystalline since the deposition was done over Si(3)N(4) layer 14. The surface of regions 28, 30 and 32 is then reoxidized, and source and drain regions 34 and 36 made by diffusion through openings made through layer 33. After reoxidation, P-type dopants are diffused into the P channel device forming regions 38, 40 and making the polycrystalline region 32 conductive.

Figs. 6-10 depict an alternate method utilizing the same basic concepts to fabricate complementary transistors. A thermal layer 10 of SiO(2) is formed on the surface of substrate 12, and regions 42 and 44 formed therein by co...