Browse Prior Art Database

Current Switch Collector Dot Decoder

IP.com Disclosure Number: IPCOM000078379D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

The decoder shown is for a monolithic memory. The object is to route a single large unit of current I5 to one of four (or more) memory array drive lines 0, 1, 2, 3. Transistor pairs T1, T2; T3, T4; T5, T6 and T7 T8, are current switches, each capable of switching one unit of current (I1 through I4) which is small compared to current I5.

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Current Switch Collector Dot Decoder

The decoder shown is for a monolithic memory. The object is to route a single large unit of current I5 to one of four (or more) memory array drive lines 0, 1, 2, 3. Transistor pairs T1, T2; T3, T4; T5, T6 and T7 T8, are current switches, each capable of switching one unit of current (I1 through I4) which is small compared to current I5.

Two address inputs ADR1 and ADR2 drive two current switches each. The collectors of the current switch transistors are wired to the output load resistors R1, R2, R3, R4 such that for each of the four combination of address input states one resistor has no current, two resistors have one unit of current and one resistor has two units of current. There is thus a difference in the four output voltages of at least one unit of current multiplied by the load resistor value.

Transistors T9, T10, T11 and T12 form a current switch whose base inputs B1, B2, B3, B4 are connected to the decoder outputs V0, V1, V2 and V3, respectively. The large unit of current I5 is thus switched to one of drive lines 0, 1, 2 or 3 depending on the state of the input addresses. This concept can be extended to drive large numbers of array drive lines.

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