Browse Prior Art Database

Making Enhancement and Depletion Mode FET's on same Chip

IP.com Disclosure Number: IPCOM000078381D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Bhatia, HS: AUTHOR [+2]

Abstract

Depletion-mode field-effect transistor (FET) devices, useful as load elements for enhancement mode FET devices, are fabricated on the same chip with the latter devices in accordance with the following method.

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Making Enhancement and Depletion Mode FET's on same Chip

Depletion-mode field-effect transistor (FET) devices, useful as load elements for enhancement mode FET devices, are fabricated on the same chip with the latter devices in accordance with the following method.

Buried N+ region 1 is ion-implanted in the P substrate underneath the FET devices shown in the figure. The buried region is brought closer to the channel region of each desired depletion-mode device, by a respective pedestal portion
2. The FETs otherwise are fabricated in the usual manner and a contact is provided for the N+ buried region.

By forward biasing the PN junction consisting of the N+ buried region and the P substrate, electrons can be injected into the channel region of each desired depletion-mode device. Where there is no pedestal portion 2, the buried region is too deep to affect the operation of the normal enhancement-mode devices.

The contoured buried region is achieved by implanting ions of appropriately tailored energies. The pedestal portion 2 being confined to the channel region avoids undesirable NPN action between the N+ buried region, the P substrate, and the N+ source and drain diffusion of the enhancement-mode devices.

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