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Set Reset Flip Flop Circuit

IP.com Disclosure Number: IPCOM000078386D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Richter, DH: AUTHOR

Abstract

The circuit diagram and accompanying logic and timing diagrams illustrate a novel set-reset flip-flop.

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Set Reset Flip Flop Circuit

The circuit diagram and accompanying logic and timing diagrams illustrate a novel set-reset flip-flop.

The circuit requires two inputs and sends out one true output Q at logic levels. The set S input operates at levels one diode drop below logic levels, while the reset R input levels result from Q downward displacement of approximately one half a diode drop from the logic levels. The timing diagram (Fig. 3) depicts the way in which the circuit operates; e.g., when S is brought up, Q will, if not already up, be brought up; when S goes back down, Q will remain up, until R is brought up, at which time Q goes back down; when R goes back down, Q will remain down until S is brought back up.

The key to this circuit's ability to operate oorrectly, is the feedback connection of the base of transistor Q3 to the cathode of diode D1. In effect, the base of transistor Q3 will take on the level of the set line when it is up. When S goes down, the current switch (formed by transistor Q1, Q2, and Q3) will be biased so that only Q3 will be on. When R comes up, Q3 will turn off and Q2 will turn on, so that current will flow through R1, whereby the output Q will go down and the base of transistor Q3 will go down to the low-level voltage of S. When R goes down, Q2 remains on, current continues to flow through R1, the output Q remains down and the base of Q3 remains at its low level. In the circuits shown, J1 and J2 are constant-current sources providing c...