Browse Prior Art Database

Read/Write Circuit for Dynamic Memories

IP.com Disclosure Number: IPCOM000078388D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

This is a circuit for writing into a monolithic memory array without the need for a separate write control signal.

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Read/Write Circuit for Dynamic Memories

This is a circuit for writing into a monolithic memory array without the need for a separate write control signal.

In order to write into the monolithic memory without a write control signal by the present circuit, a selected one of the bit/sense lines is brought to an up level while the other one is brought to a down level. Assuming for purposes of example that a logical "1" is to be written, then the bit/sense line B/1 is brought to a down level while the B/0 line is brought to an up level. In the sequence of pulses shown, the restore pulse R turns on transistors 33, 99 and 35 charging the data output node, the data input node from selected storage cells, and the gate of transistor 38 to up levels. VH and VR are both positive voltage levels with VH being slightly higher than VR. Under this stated set of conditions, when the CSX pulse at CSX1 comes to an up level, the gate of transistor 100 is charged to an up level, although for no effective purpose in the case when either transistor 36 or transistor 37 is off, due to one of the bit/sense lines being at a down level.

The occurrence of the CS pulse will then be transmitted through transistor 38, providing an up level signal at the control output node to the bit decoder. This will turn on the write gate of selected cells. Also, when the control output goes up, transistor 39 is conditioned on. Transistors 34, 41 and 42 are also turned on, but for no purpose during a write operation. Transistor 40 is off because of the down level of the B/1 line in the present example, so that the data output node cannot discharge through transistor 40, even though transistor 39 is conditioned on. The data output node is therefore maintained at an up level, indicating that a 1 is to be written.

If the polarity of the bit/sense lines had been reversed, the same set of conditions would have prevailed throughout the circuit except that when the B/1 line is up and the B/0 line is down, then the data output node is discharged and a down level is provided as the data to be written. In the sequence of pulses shown, the occurrence of the phase pulse turns transistor 102 on discharging the gate of transistor 38 to a down level. The occurrence of the CSX2 pulse discharges the control output n...