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Associative Memory Sequencing Arrangement

IP.com Disclosure Number: IPCOM000078407D
Original Publication Date: 1972-Dec-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

The arrangement for sequencing control, shown schematically in the figure, allows a large-capacity associative memory to be built modularly of sections, using multiple associative-array chips of a single type.

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Associative Memory Sequencing Arrangement

The arrangement for sequencing control, shown schematically in the figure, allows a large-capacity associative memory to be built modularly of sections, using multiple associative-array chips of a single type.

As in conventional design, "match" latches are provided on each chip, to be reset to "0" prior to an associative search and set to "0" to mark the word sections on the chip matching to the search criterion. Match latches on a chip are (instead of being used to drive a "ripple" chain of AND gates as in conventional design) connected together to form a ring-shift register (MLRR). To detect full matches on the basis of these marked sectional matches on the various chips, the MLRR's are sensed at their first position and the signals are fed into an AND circuit. When the AND output is 1, an access operation to the matching word is carried out and subsequently the MLRR's are shifted once in synchronism. When the output is 0, only the shifting is done. This sensing for access or nonaccess and the shifting are repeated, until the MLRR's have been shifted around once completely.

For the sequencing control of accessing the matching words, one after another, in the associative array (as well as the pertaining words in a nonassociative array which may be attached as a capacity extension), either the shift pulses are counted by a counter whose content is then used as a "word address" to be decoded to select a word line, or (as s...