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Method for programmable page tables for 64-bit architectures

IP.com Disclosure Number: IPCOM000078431D
Publication Date: 2005-Feb-25
Document File: 4 page(s) / 468K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for programmable page tables for 64-bit architectures. Benefits include improved functionality.

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Method for programmable page tables for 64-bit architectures

Disclosed is a method for programmable page tables for 64-bit architectures. Benefits include improved functionality.

Background

              The conventional page table architecture for a microprocessor consists of a page table base register. It contains the address of the top-level page directory and zero or more levels of additional page directories, the final of which are called page tables. Page directories and page tables are very similar in structure except that certain bits differ. Page directories point to other page directories or page tables. Page tables contain the final page table entry containing the information for the page being accessed. For example, for some 32-bit processors, a 2-level page table maps a 32-bit virtual address onto a 32-bit physical address. A top-level page directory contains pointers to 1024 page tables, each containing page table entries for 1024 4-KB pages. The entire memory occupied by a fully populated page table is 4 KB for the top level page directory plus 4 MB for the 1024 4-KB page tables.

              For some 64-bit architectures, the size of the page tables grows exponentially. The 64-bit extensions to a 32-bit page table use a 4-level page table that maps to a 48-bit virtual address onto a 40-bit physical address, well short of a full 64-bit address. A fully populated page table occupies over 4 TB.

General description

              The disclosed method is programmable page tables for 64-bit architectures. The number of strides (levels) in the page table is programmable by system software.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing programmable page tables for 64-bit architecture

•             Improved functionality due to providing adjustable address sizes

•             Improved functionality due to enabling embedded microcontrollers to use 64-bit arithmetic with a small amount of physical memory

•             Improved functionality due to enabling a microcontroller to be used for a variety of purposes

Detailed description

              The disclosed method includes page tables that are programmable for mapping an address space from the megabyte (MB) range all the way to 64-bit, 16 ‘Exa’ Byte (EB) range and beyond. The method has a system control register that contains the number of layers the page table occupies. The processor reads this value to determine how many layers to expect in the page table. As a result, the size of the address space mapped by virtual memory can be programmed by system software rather than being fixed as it is conventionally. This capability enables embedded microcontrollers to use 64-bit arithmetic without having a very large page table when they might have a small amount, such as 16 MB, of physical memory.

              For some 32-bit architectures, the processor uses a two-layer (2-stride) page table. The 32-bit virtual address is d...