Browse Prior Art Database

Dynamic Error Correction Using Twin Rail Design

IP.com Disclosure Number: IPCOM000078434D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Carnevale, RJ: AUTHOR [+2]

Abstract

With more emphasis being placed on reliability, availability, serviceability (RAS) in system design, it becomes more desirable to integrate into systems designs error-correction mechanisms where feasible. Described is an economical and simple mechanism to satisfy one of the RAS objectives.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 65% of the total text.

Page 1 of 2

Dynamic Error Correction Using Twin Rail Design

With more emphasis being placed on reliability, availability, serviceability (RAS) in system design, it becomes more desirable to integrate into systems designs error-correction mechanisms where feasible. Described is an economical and simple mechanism to satisfy one of the RAS objectives.

In present designs, single bit errors are detected but not corrected when moving data within the data flow of a CPU (central processing unit) or across interfaces. The circuit shown in the figure dynamically detects and corrects single-bit errors and includes:
A True bit input
B Complement bit input
Z Input "EQUIVALENCE" block, determines the validity of T/C (true/complement) inputs A and B

Y Parity check logic which checks for odd parity on a byte X Compares a byte parity error (output 2) with the proper bit in error (output 1), to provide an invert signal to

error corrector W

W Error corrector, an EQUIVALENCE block.

The EQUIVALENCE blocks Z and W produce positive outputs for an even number of positive inputs A and B, i.e. if both inputs are positive or both are negative, the output is positive.

The XOR (exclusive OR) block Y produces positive output for an odd number of bits in a logical "1" state.

During normal operation without an error, inputs A and B are complementing and output 1 is negative. The parity checking output 2 is positive. X will not be satisfied, and output 3 is negative. The complementing input B is routed to one ...