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Control Circuit for Stored Charge Memory Arrays

IP.com Disclosure Number: IPCOM000078439D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Dailey, JR: AUTHOR [+2]

Abstract

Stored-charge arrays of the metal nitride oxide semiconductor (MNOS) type require selective application of appropriate voltage levels to the array cells. This is necessary to perform operations of "ERASE", "WRITE", and "READ" within the array. Each bit position of the array usually consists of a single MNOS type of device whose gate is connected to other device gates to form a WORD line, and whose drain and source terminals are each attached to BIT lines (Fig. 1.). Thus, there are two bit lines per bit column required.

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Control Circuit for Stored Charge Memory Arrays

Stored-charge arrays of the metal nitride oxide semiconductor (MNOS) type require selective application of appropriate voltage levels to the array cells. This is necessary to perform operations of "ERASE", "WRITE", and "READ" within the array. Each bit position of the array usually consists of a single MNOS type of device whose gate is connected to other device gates to form a WORD line, and whose drain and source terminals are each attached to BIT lines (Fig. 1.). Thus, there are two bit lines per bit column required.

The problem of selectively applying the conditions of the table in Fig. 1 to the array cells can be alleviated by the control circuit of Fig. 2.

Operation is as follows:
1) (ERASE) - For the ERASE operation, ground potential is

applied at nodes x and y. This causes devices 1, 4, 5

to be reverse biased keeping them OFF, while devices 2

and 3 are forward biased and turn ON. This couples -V

to both A and B bit lines satisfying the erase

requirements.
2) (WRITE) - For the WRITE operation, -V is applied to

nodes x and y. This causes devices 2, 3 to be turned

OFF and devices 1, 4 and 5 to turn ON, which couples

a ground potential to bit lines A and B satisfying the

write requirement.
3) (READ) - A READ operation requires that node x have -V

and node y have ground potential applied. This condition

causes devices 2, 3 to turn OFF and devices 1 and 4 to

turn ON. Device 5 is also biased OFF. Thus, bit line

B is...