Browse Prior Art Database

Flexible Read Only Read/Write Memory Partition

IP.com Disclosure Number: IPCOM000078442D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Patzer, WJ: AUTHOR

Abstract

In computer storage systems, the program size and/or the division between read-mostly and read/write sections of storage changes, between the time the initial design is established and the time the system becomes fully operational. If either the capacity of the read-mostly or read/write sections of storage be exceeded, it is generally very difficult to modify the storage design and it becomes necessary to optimize the programming at considerable cost. The storage system shown in Fig. 1 includes a read-mostly storage array 10 which implements all storage addresses from zero to the maximum amount of storage required. The system also includes a read/write array 12 of nominal size. The shaded portion of read-mostly array 10 has addresses identical to those assigned to the read/write array 12.

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Flexible Read Only Read/Write Memory Partition

In computer storage systems, the program size and/or the division between read-mostly and read/write sections of storage changes, between the time the initial design is established and the time the system becomes fully operational. If either the capacity of the read-mostly or read/write sections of storage be exceeded, it is generally very difficult to modify the storage design and it becomes necessary to optimize the programming at considerable cost. The storage system shown in Fig. 1 includes a read-mostly storage array 10 which implements all storage addresses from zero to the maximum amount of storage required. The system also includes a read/write array 12 of nominal size. The shaded portion of read-mostly array 10 has addresses identical to those assigned to the read/write array 12.

When power is turned on, read/write array 12 contains random information.

The address counter 14 is set to the lowest address of the overlapped read/write and read-mostly arrays. Data is then read from the read-mostly storage addresses to the read/write array for initialization. This operation continues until the overlapped portion of the read-mostly array 10 has been copied into corresponding address locations in read/write array 12.

After the power on copy is completed, storage system reverts to a mode in which it is responsive to a processor. In that mode, any addresses received from address decoder 14 which might access either t...