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Test Pattern Generator

IP.com Disclosure Number: IPCOM000078449D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 4 page(s) / 55K

Publishing Venue

IBM

Related People

Muehldorf, EI: AUTHOR

Abstract

To functionally test large-scale integrated logic circuits having "r" test points, a test pattern generator is used which converts a serial data stream of "n" compacted pattern messages into a sequence of "n" parallel digital patterns. Functional testing tests the functional behavior of a digital integrated circuit, by applying a sequence of impact words at nominal voltage levels and checking the corresponding output words.

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Test Pattern Generator

To functionally test large-scale integrated logic circuits having "r" test points, a test pattern generator is used which converts a serial data stream of "n" compacted pattern messages into a sequence of "n" parallel digital patterns. Functional testing tests the functional behavior of a digital integrated circuit, by applying a sequence of impact words at nominal voltage levels and checking the corresponding output words.

In this comparison type tester, a binary pattern is applied to sample device under test 1 and the same time to standard device 2 having the same truth table as device 1. The output are compared by exclusive OR's 3 and a defect signal is generated from OR 3 when the outputs differ. The comparison tester comprises clock 4, which generates reference timing signals for test pattern data source 5 and test pattern generator 6 (shown in the upper right part of the drawing, over the dash line). Test pattern data source 5 processes test pattern instructions provided by the designer and generates the test pattern message which comprise the input data stream, which is transmitted over input channel 7 to test pattern generator 6. Test pattern generator 6 generates a sequence of gating pulses over output lines 8. The gate pulses serve to connect selective test points on sample device 1 and standard device 2 to signal pulse generator 9. When a set of gating pulses are generated on output lines 8, a trigger signal is generated by the test pattern generator on line 10 which triggers signal pulse generator 9. The gating pulses on output lines 8 open selected ones of AND gates 11, and the signal pulse from signal pulse generator 9 is conducted to the desired input test points on sample device 1 and standard device 2, respectively.

If the output signal pattern from sample device 1 is not identical to the output signal pattern from standard device 2, exclusive OR gates 12 corresponding to the output line will propagate a defect signal to defect recorder 13. Defect recorder 13 records the pattern of gating pulses on output lines 8 which reveal the defective logical function in sample device 1, and then a sample rejection decision is made by decision means 14. The designer has established acceptance criteria for sample devices under test and has entered these criteria as machine instructions into the decision means 14. If the acceptance criteria are met, the testing will proceed to determination and the device will be deemed to have passed its functional testing. If the acceptance criteria is not met, decision means 14 will generate a reject signal, sample device 1 under test will be removed from the test station, the next sample device will be indexed, and the functional testing sequence will be restarted.

Test pattern generator 6 is a Shannon-Fano decoder pattern generator. It is a sequential digital pattern generator for converting a serial input data stream of "n" compacted pattern messages into a sequence...