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Linear Feedback Shift Register Sequence Generator for Specified Sequences

IP.com Disclosure Number: IPCOM000078451D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Hong, SJ: AUTHOR [+4]

Abstract

This sequence generator is a fast and economic way to generate any specified binary sequences of array length. These sequences can be used for testing, such as for large-scale integrated (LSI) chips.

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Linear Feedback Shift Register Sequence Generator for Specified Sequences

This sequence generator is a fast and economic way to generate any specified binary sequences of array length. These sequences can be used for testing, such as for large-scale integrated (LSI) chips.

Fig. 1 shows how the specified binary sequences of length 2/r/ or less can be generated. The sequence source generator is a r-stage linear feedback shift register, as shown in the dotted line portion. The linear feedback shift register is characterized by a primitive polynomial. This characterization is done by specifying the value of a(0), a(1), ..., a(r-1). If a(i)=1 (i = 0,1,...,r-1), x/i/is connected directly to the Mod 2 adder. If a(i)=0, there is no connection. The property of a primitive polynomial is that the corresponding shift register generates all 2/r/-1 patterns of r digits (except the all-zero pattern). For example, if r=4, we can choose a primitive polynomial 10X0X/4/ which will generate all 15 nonzero patterns of 4-bit length.

The true and complement output of these r-stage shift cells are sent to a decoder. The decoder contains 2/r/-1 AND gates. Its output will follow exactly the patterns of the basic sequence generator. Table 1 shows the case of r=4.

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The 2/r/-1 columns of the matrix M provide inputs to the k OR gates in a selective manner, to generate the specified sequences T(1), T(2), ... T(k). This selection is done by a pluggable wire connection unit which...