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Multiprocessing Computing System With Task Assignment at the Instruction Level

IP.com Disclosure Number: IPCOM000078464D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Kurtzberg, JM: AUTHOR [+3]

Abstract

This computing system comprises a plurality of separate processors. Control means for providing sequences of instructions to processors for execution, includes means for sharing with all processors main storage, local storage, and a plurality of interlocks for preventing unwanted interaction between the plurality of processors. Each control means further includes means for sharing a micro-instruction store. The micro-instruction store contains control sequences for controlling the sequences of operations of each of the plurality of processors. Means are included in the control means for accessing successive machine instructions provided to the multiprocessing system and stored in main storage. The instructions are written in machine language of the desired processor.

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Multiprocessing Computing System With Task Assignment at the Instruction Level

This computing system comprises a plurality of separate processors. Control means for providing sequences of instructions to processors for execution, includes means for sharing with all processors main storage, local storage, and a plurality of interlocks for preventing unwanted interaction between the plurality of processors. Each control means further includes means for sharing a micro-instruction store. The micro-instruction store contains control sequences for controlling the sequences of operations of each of the plurality of processors. Means are included in the control means for accessing successive machine instructions provided to the multiprocessing system and stored in main storage. The instructions are written in machine language of the desired processor. Means including the micro-instruction store and appropriate decoders are provided, for converting machine language instructions into a micro-instruction sequence for executing it in one of the processors.

Means are provided for determining if all or part of an accessed instruction can be performed immediately, or must await the performance of a part of a previous instruction. Interlocks are embodied in latches whereby before certain micro-instruction operations can be performed by a processor, it must be determined whether or not another processor is performing a related operation. Means are provided for certain testing situations wherein the interlock is both tested and set in a single-processor cycle to prevent a race condition existing, wherein two or more processors might try to make the same test substantially concurrently.

A conventional sequence of machine language instructions is stored in main storage. Alternate processors will access successive instructions. Thus, a single-instruction stream is capable of being executed in a highly efficient and parallel manner. If an instruction requires the result of a previous instruction, controls are provided for preventing the subsequent processor from performing the operation until all required ope...