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Testing MOSFETS for Shorts

IP.com Disclosure Number: IPCOM000078479D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Puri, P: AUTHOR

Abstract

Linear load metal-oxide semiconductor field-effect transistor (MOSFET) chips can be tested for gate shorts, drain-to-source shorts, contact shorts, metal signal-to-ground shorts, diffusion signals-to-source shorts etc., by monitoring current through drain power supply. All devices on the chip can be turned off by setting the gate voltage of the load device, substrate voltage to the normal operating values, and drain supply equal to the lowest expected threshold voltage. Leakage current of nanoamps range flows through the drain supply. Fault current several magnitudes higher than leakage current will flow, if a short such as mentioned before occurs on the chip.

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Testing MOSFETS for Shorts

Linear load metal-oxide semiconductor field-effect transistor (MOSFET) chips can be tested for gate shorts, drain-to-source shorts, contact shorts, metal signal-to-ground shorts, diffusion signals-to-source shorts etc., by monitoring current through drain power supply. All devices on the chip can be turned off by setting the gate voltage of the load device, substrate voltage to the normal operating values, and drain supply equal to the lowest expected threshold voltage. Leakage current of nanoamps range flows through the drain supply. Fault current several magnitudes higher than leakage current will flow, if a short such as mentioned before occurs on the chip. The following equation can be used to determine the fault current and hence the rejection criteria for the chip: I = delta mW over L (V(G) - V(THL) - V(ds)) V(ds) over 2 where; 1 = Fault current delta m = Normalized transconductance in umhos V(THL) = Threshold Voltage of the load device V(ds) = Drain to source voltage W = Width of the load device L = Length of the load device V(G) = Gate Voltage of the load device.

Creating two voltage planes for saturated load MOSFET chips permits fault currents to flow to detect gate oxide shorts.

Fig. 1 shows a portion of a large scale integrated circuit, showing FET's A, B and C connected in a NOR circuit. Fig. 2 shows a chip layout of Fig. 1. Two distinct voltage planes are created on the chip by satisfying the following conditions: V(DD) = drain supply = 5.0 volts V(GD) = bus connecting all sources (called ground bus) =...