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Digital Validity Checking

IP.com Disclosure Number: IPCOM000078488D
Original Publication Date: 1973-Jan-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Hoffman, GF: AUTHOR

Abstract

Many digital machines employ a bus having groups of control or signal lines in which only one line of each group is allowed to be active at any one time. System 10 produces a validity signal when this condition is met. System 10 is extendible to any number of groups, and to any number of lines in a group, by a regular structure which is easily integrable and which avoids high-loading factors on gates within the system.

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Digital Validity Checking

Many digital machines employ a bus having groups of control or signal lines in which only one line of each group is allowed to be active at any one time. System 10 produces a validity signal when this condition is met. System 10 is extendible to any number of groups, and to any number of lines in a group, by a regular structure which is easily integrable and which avoids high-loading factors on gates within the system.

For illustrative purposes, bus 11 is assumed to have three groups A, B and C of five lines each. A-Group Module 20 receives inverted signal inputs A1 through A5 from bus 11 to produce a validity signal on output 22, if one and only one of these five bus lines is in a "true" state. Input 21 is grounded if there are no previous groups to be checked in bus 11. B-Group Module 30 receives inverted signals B1 through B5 and has input 31 connected to output line 22 of the previous module 20. Module 30 produces an output on line 32 if one and only one of the B-group inputs is active, and if an A-group validity signal appears on input 31. Similarly, C-Group Module 40 produces a validity signal on output 42 if only one of the C-group bus lines is active and if input 41 receives a validity signal from module 30. Since the validity signals on lines 22, 32 and 42 reveal the status of all preceding groups of bus lines, the last output 42 is the system output, and indicates whether one and only one line of each group is active. Additional bus groups may be tested merely by cascading additional modules to module 40.

The internal structure of all modules is identical. Module 30, for example, contains three diagonal ranks 50, 60, 70 of gates, regardless of the number of bus lines in the group.

When none of the bus lines in group B is "true", all of the inputs B1-B5 are active, so all of the AND's 51-53 in rank 50 are enabled. Because of the inverters 61-64, however, all of the AND's 65-68 are disabled. Therefore, all of the gates 71-79 of rank 70 are disab...